1. Field of the Invention
The present invention relates to signal processing systems. More specifically, the invention relates to filtering systems for usage in various applications including decimators.
2. Description of the Related Art
Signal processing systems often include digital filters for performing various filtering operations. Digital filters are classified into two types, infinite impulse response (IIR) filters and finite impulse response (FIR) filters. FIR filters are commonly used to perform digital filtering functions. For causal systems with finite-duration impulse responses, filters generally process an input signal according to a nonrecursive computational algorithm.
Accordingly, digital filters generally perform a large number of computations (e.g., multiplication) and require a large number of storage elements (e.g., registers) for temporarily storing computed variables (e.g., state variables) in carrying out the computations. The number of storage elements and computations carried out by a digital filter directly effects the device's size, speed, and power consumption. As the complexity of digital filters increase, the number of computation and the number of registers required tend to increase. At the same time, improved performance is continually expected from digital filters.
For these reasons, it is desirable to improve the computational efficiency and speed (e.g., reduce the number of computations) and reduce the number of storage elements required in FIR filters. It is also desirable to have a scalable filter architecture that can accommodate different complexity levels and be capable of achieving the required performance.